Flip-chip assemblies are formed by combining two separate chips. Usually one of the chips contains spacers that offset the facing surfaces of each of the chips. Micro-electromechanical systems (MEMS) devices for optical applications typically require the fabrication of arrays of micro-mirrors that are tilted using electrostatic control using a set of electrodes located beneath, and/or adjacent to, the micro-mirror. The gap between the mirror and the electrodes is a crucial characteristic of the MEMS device because it determines, among other things, the maximum achievable tilt angle. This is because, if the plate of the micro-mirror is located too close to the substrate on which the electrodes are mounted with respect to the size of the mirror plate, the plate will impact on the substrate, thus limiting the range of tilt.
In the following descriptions, the term “wafer” and the term “chip” may be used interchangeably, assuming there is only one chip per wafer. If there is more than one chip per wafer, than then the term “chip” refers to a smaller unit that is separated from the wafer by a dicing operation. Such dicing operation may be performed prior to, or after, formation of the flip-chip assembly.
In the prior art, a flip-chip arrangement is not required for small gaps. Instead, in a single wafer, a so-called “sacrificial” film is formed where the gap is ultimately desired, and the sacrificial film is etched away during manufacturing to release the mirror plate. This approach is only practical for thin sacrificial films, e.g., on the order of few microns, because mechanical stress develops in thicker sacrificial films, causing destruction of the device. This approach is thus of limited use when large gaps are required, e.g., for larger micro-mirrors with larger angular tilt range requirements.
To achieve larger gaps, the most common technique is to employ a flip-chip arrangement. Typically, the moving portion of the device is formed on one wafer, while the electrodes are formed on another. The wafer on which the moving portion is formed is typically a silicon on insulator (SOI) type of wafer. An exemplary SOI wafer is made of three layers. The first layer is a so-called “handle” wafer layer, which is silicon. The second layer, a buried oxide layer (BOX) which is also known as the “sacrificial layer”, is an insulator. The third layer, the “mechanical” layer, is also silicon, although it a) is typically much thinner than handle wafer layer and b) may be referred to as the device layer. The wafer on which the moving portion is formed is etched to remove portions of its handle wafer and its BOX layer so as to free the moving structure. The remaining portion of the handle wafer is then anodically, i.e., field assisted, or fusion bonded to the electrode containing wafer, with the result being that the thickness of the handle wafer defines the gap between the electrodes and the moving portion. However, this approach limits considerably the available materials and process sequences that may be employed.
For example, for anodic bonding at least one material must be insulating and the thermal expansion coefficients of the two materials must be nearly the sane. Suitable such materials are silicon and silicon oxide. The surfaces of the two materials should also be clean and polished smooth. To achieve the anodic bond a relatively large voltage is applied across the two pieces to be bonded at an elevated temperature, e.g., between 300° C. and 450° C. Because of the necessity of high temperature, unwanted reactions may result with any metalized section of the device being formed, and so anodic bonding is not especially suitable to forming MEMS devices such as micro-mirrors.
Alternatively, fusion, i.e., direct, bonding does not require applied voltages or that either material be an insulator. Bonding is achieved primarily through chemical reactions between materials on the two surfaces. The two chips are mated together at room temperature and then annealed at high temperatures, e.g., on the order of 1100° C. for silicon, to increase the bond strength.
In order to survive either anodic or fusion bonding, the moving parts of the device being assembled have to be freed only after the bonding is completed. This requires that both chips be compatible with the etchant used to release the moving parts. Furthermore, since the thickness of one of the chips is determinative of the final gap, use of these bonding techniques limits the gap sizes to relatively large gaps, e.g., larger than 200 microns, because the flip-chip wafers must be at least that thick in order to handle them through the various process steps without breaking them.
Polyimides (PI) are a polymerized organic polymer which has been used in various prior art applications, e.g., to provide a protective coating for integrated circuits or as a thick dielectric. Various polyimide compound formulations are available, where various additives are combined with the polyimide to provide an overall material with particular prescribed characteristics. Use of polyimide as a spacer is taught in the prior art. For example, U.S. Pat. No. 4,923,421 teaches the use of fully baked polyimide as a spacer between the display face and the cathode surface of a flat panel display. However, in the prior art the polyimide functions only as a spacer. Other techniques are employed to keep the spaced apart elements together, e.g., in U.S. Pat. No. 4,923,421 the display face and the cathode surface are sandwiched together and sealed to form the final display.
In U.S. patent application Ser. No. 10/371,258 it was recognized that not only can polyimide be used as a spacer, it can also be used to bond together the elements that it is spacing apart, e.g., the various wafers that are assembled together to form a flip-chip. This is achieved by constructing the spacer on at least one of the wafers as is typically done, except that prior to performing the final curing of the polyimide precursor to form the final polyimide, the flip-chips are aligned in a flip-chip or wafer bonder and placed in contact under pressure at a temperature slightly higher than the soft-bake temperature as specified by the polyimide manufacturer of the polyimide precursor for few minutes to promote tackiness. A useful temperature slightly higher than the soft-bake temperature, when the soft-bake temperature is, for example, 100° C., was found to be about e.g., 120° C., and a useful contact pressure was found to be 40 grams per square millimeter. This holds the flip-chips together, and the combined structure is then baked to fully cure the polyimide precursor into polyimide and complete the bonding of the flip-chips to the polyimide.
Advantageously, the maximum temperature of the bonding process need be no higher than the temperature needed to achieve the final curing of the polyimide, e.g., 200° C., which is considerably lower than the temperatures required for prior art flip-chip bonding procedures. Further advantageously, the moving parts may be released before or after the flip-chips are bonded together, thus allowing the processes employed for each chip to be independently optimized.
Polyimide spacers may be made to achieve gap heights ranging from about 5 microns to about 200 microns. To achieve such gap heights the “top” chip is typically assembled with its handle “up”. If the “top” chip is mounted handle “down” the gap will be the height of the polyimide spacers plus the thickness of the wafer of the “top” chip.
Note that polyimide spacers can be made on each wafer, and the spacers on each wafer aligned and bonded to create combined spacers, thus doubling the maximum spacing achievable with a polyimide spacer on only one of the waters.